1 fn6478.2 5962-0721301qx, 5962-0721302QX, 5962-0721303qy 500mhz rail-to-rail amplifiers the 5962-0721301qxc, 5962-0721302QXc and 5962-0721303qyc are fully dla smd compliant parts and the smd data sheets are availa ble on the defense logistics agency land and maritime (dla) website ( http://www.landandmaritime.dl a.mil/downloads/milspec/sm d/07213.pdf ). the 5962-0721301qxc is electrically equivalent to the el8202, the 5962-0721302QXc is electrically equivalent to the el8203, and the 5962-0721303qyc is electrically equivalent to the el8403. reference equivalent ?el? data sheet for additional information. these parts are dual and quad rail-to-rail amplifiers with a -3db bandwidth of 500mhz and slew rate of 600v/s. running off a low supply current of 13.5ma per channel, the 5962-0721301qxc, 5962-0721302QXc, and 5962-0721303qyc also feature inputs that go to 0.15v below the v s - rail. the 5962-0721301qxc and 5962-0721302QXc are dual channel amplifiers. the 5962-0721303qyc is a quad channel amplifier. the 5962-0721301qxc includes a fast-acting disable/power-down circuit with a 25ns disable and a 200ns enable, the 5962-0721301qxc is ideal for multiplexing applications. features ? 500mhz -3db bandwidth ? 600v/s slew rate ? supplies from 3v to 5.5v ? rail-to-rail output ? input to 0.15v below v s - ? fast 25ns disable (5962-0721301qxc only) applications ? video amplifiers ? portable/hand-held products ? communications devices ordering information part number part marking package pkg. dwg. # 5962-0721301qxc 07213 01qxc 10 ld flat pack k10.a 5962-0721302QXc 07213 02qxc 10 ld flat pack k10.a 5962-0721303qyc 07213 03qyc 14 ld flat pack k14.a note: these intersil pb-free herm etic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. pinouts 5962-0721301qxc (10 ld flatpack) top view 5962-0721302QXc (10 ld flatpack) top view 5962-0721303qyc (14 ld flatpack) top view ina+ vs- ceb vs+ outb inb+ 10 9 8 7 6 2 3 4 5 1 cea ina- inb- outa ina+ vs- nc vs+ outb inb 10 9 8 7 6 2 3 4 5 1 nc ina- inb- outa outa ina+ vs+ ind+ vs- inb 14 13 12 11 10 2 3 4 5 1 ina- outd inc+ ind- inb inc- outb outc 7 9 8 6 data sheet november 30, 2011 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2007, 2011. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn6478.2 november 30, 2011 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = +25c) thermal information supply voltage from v s + to v s - . . . . . . . . . . . . . . . . . . . . . . . . 5.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . v s + +0.3v to v s - -0.3v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v continuous output current . . . . . . . . . . . . . . . . . . . . 20ma/op amp power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 74.3mw/op amp storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . .-55c to +125c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications v s + = 5v, v s - = gnd, t a = +25c, v cm = 2.5v, r l to 2.5v, a v = 1, unless otherwise specified. parameter description conditions min typ max unit input characteristics r in input resistance common mode 3.5 m c in input capacitance 0.5 pf output characteristics r out output resistance a v = +1 30 m i out linear output current 65 ma enable (5962-0721301qxc only) t en enable time 200 ns t ds disable time 25 ns v ih-enb enable pin voltage for power-up 0.8 v v il-enb enable pin voltage for shut-down 2 v ac performance bw -3db bandwidth a v = +1, r f = 0 , c l = 2.5pf 500 mhz a v = -1, r f = 1k , c l = 2.5pf 140 mhz a v = +2, r f = 1k , c l = 2.5pf 165 mhz a v = +10, r f = 1k , c l = 2.5pf 18 mhz bw 0.1db bandwidth a v = +1, r f = 0 , c l = 2.5pf 35 mhz peak peaking a v = +1, r l = 1k , c l = 2.5pf 2 db gbwp gain bandwidth product 200 mhz pm phase margin r l = 1k , c l = 2.5pf 55 sr slew rate a v = 2, r l = 100 , v out = 0.5v to 4.5v 600 v/s t r rise time 2.5v step , 20% to 80% 4 ns t f fall time 2.5v step , 20% to 80% 2 ns os overshoot 200mv step 10 % t pd propagation delay 200mv step 1 ns t s 0.1% settling time 200mv step 15 ns dg differential gain a v = +2, r f = 1k , r l = 150 0.01 % dp differential phase a v = +2, r f = 1k , r l = 150 0.01 e n input noise voltage f = 10khz 12 nv/ hz i n + positive input noise current f = 10khz 1.7 pa/ hz i n - negative input noise current f = 10khz 1.3 pa/ hz e s channel separation f = 100khz 95 db 5962-0721301qx, 5962-0721302q x, 5962-0721303qy
3 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6478.2 november 30, 2011 simplified schematic diagram pin descriptions 5962-0721301qxc (10 ld flatpack) 5962-0721302QXc (10 ld flatpack) 5962-0721303qyc (14 ld flatpack) name function 1, 5 1, 5 3, 5, 10, 12 in+ non-inverting input for each channel 2, 4 ce enable and disable input for each channel 3 3 11 vs- negative power supply 6, 10 6, 10 2, 6, 9, 13 in- inverting input for each channel 7, 9 7, 9 1, 7, 8, 14 out amplifier output for each channel 8 8 4 vs+ positive power supply 2, 4 nc not connected in+ in- i 1 i 2 r 6 r 3 r 1 r 2 q 1 q 2 r 7 v bias1 q 5 q 6 r 8 q 7 q 8 r 9 q 3 q 4 r 4 r 5 v s- out v bias2 v s+ differential to drive generator single ended 5962-0721301qx, 5962-0721302q x, 5962-0721303qy
4 fn6478.2 november 30, 2011 5962-0721301qx, 5962-0721302q x, 5962-0721303qy ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m d k10.a mil-std-1835 cdfp3-f10 (f-4a, configuration b) 10 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.290 - 7.37 3 e 0.240 0.260 6.10 6.60 - e1 -0.280-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n10 10- rev. 0 3/07
5 fn6478.2 november 30, 2011 14 ld flatpack package outline drawing notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and fini sh thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f-2a, configuration b) 14 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 -0.290-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n14 14- rev. 0 5/18/94 5962-0721301qx, 5962-0721302q x, 5962-0721303qy
|
